Bonding of III-V semiconductors on patterned Si for photonicsThursday (29.09.2016) 09:15 - 09:45 Part of:
Direct bonding of III-V semiconductors on silicon has recently become a promising technology for the fabrication of hybrid photonic integrated circuits (PICs). In such hybrid PICs, active optical functions (amplification, emission) are ensured by the direct-gap III-V semiconductor and passive functions (guiding, switching) by the Si guiding layer. One particularly attractive feature of hybrid III-V/Si platforms is the possibility to densely integrate a variety of advanced optical functions in the guiding layer using sub-100 nm patterns in the silicon. Nano-patterning the silicon surface may, however, weaken the adhesion of the III-V semiconductor to silicon, potentially making the hybrid bonded stack subject to debonding in subsequent processing steps, such as cleaving. In this context, quantitatively assessing the adhesion of the III-V to Si in a patterned area and comparing it against the adhesion in a nearby unpatterned area can provide one with feedback useful for improving the patterning , post-patterning surface preparation, or bonding processes. Ultimately, such measurements can allow one to propose optimal designs for advanced embedded optical functions in hybrid III-V/Si PICs. Instrumented nanoindentation, Atomic Force Microscopy and Scanning Transmission Electron Microscopy have been combined ex situ to study the adhesion of thin InP membranes to bulk (100) silicon substrates but also to sub-100nm patterned (100) silicon substrates [1,2].
 K. Pantzas, E. Le Bourhis, G. Patriarche, A. Itawi, G. Beaudoin, I. Sagnes and A. Talneau Eur. Phys. J. Appl. Phys. 65 (2014) 20702
 K. Pantzas, E. Le Bourhis, G. Patriarche, D. Troadec, G. Beaudoin, A. Itawi, I. Sagnes and A. Talneau Nanotechnology 27 (2016) 115707